1. Field of the Invention
The present invention relates in general to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a buried conductive layer which is connected to a source/drain of MOS transistor and extends over a gate electrode of the MOS transistor and a method for manufacturing the same.
2. Description of the Related Art
In recent years, as high integration and scale down (shrink) of a semiconductor device have progressed, the alignment margin in the photolithography process for a contact hole which is formed in order to connect a source/drain of a MOS transistor and a wiring layer to each other is being decreased. In addition, the aspect ratio of the contact hole is also being increased. Now, the aspect ratio is defined by the ratio of a depth to a diameter of the contact hole. From the foregoing, the technique is adopted in which the source/drain of the MOS transistor and the wiring layer are not directly connected each other, but are indirectly connected to each other through a buried layer (an extraction electrode) formed on the source/drain.
Now, the process of manufacturing a MOS transistor employing that baried conductive layer will hereinbelow be described simply with reference to FIGS. 1A to 1E.
Firstly, as shown in FIG. 1A, after a field oxide film 102 has been formed in a region to be an isolation region of a silicon substrate 101 by utilizing the well known LOCOS (Local Oxidation of Silicon) method, a gate oxide film 103 is formed in an active region surrounded by the field oxide film 102 by the thermal oxidation method. Thereafter, a polycrystalline silicon containing phosphorus or arsenic and a silicon oxide film 104 are formed in this order by the CVD method, and those films are then subjected to the anisotropic etching with a photo resist film (not shown), which was formed so as to have a gate electrode pattern by the photolithography technology, as an etching mask, thereby forming a gate electrode 105 formed of that polycrystalline silicon film. In addition, the impurity ions are implanted into the unmasked region with the gate electrode 105 as a mask, thereby forming a pair of lightly doped impurity diffusion layers 106 in surface portions of the silicon substrate 101 on the both sides of the gate electrode.
Next, as shown in FIG. 1B, after a silicon oxide film has been formed on the whole surface of the substrate 101, the silicon oxide film is selectively etched away by the anisotropic etching, thereby forming a side wall oxide film 107 on each of both side faces of the gate electrode 105 and the silicon oxide film 104 by the anisotropic etching. Incidentally, a portion of the gate oxide film 103 formed on the region which is not covered with the gate electrode 105 or the side wall oxide film 107 is removed concurrently with the selective etching of that silicon oxide film.
Nest, as shown in FIG. 1C, a polycrystalline silicon film 108 containing phosphorus or arsenic is formed on the whole surface of the silicon substrate 101 by the CVD method. This polycrystalline silicon film 108 will become a buried conductive layer later. Thereafter, the impurity ions are implanted into the unmasked region with both the gate electrode 105 and the side wall oxide film 107 as a mask, thereby forming a pair of highly doped impurity diffusion layers 109 as a source and a drain in the surface regions of the silicon substrate 101 on the both sides of the gate electrode 105.
Next, as shown in FIG. 1D, after a photo resist film 110 has been applied to the polycrystalline silicon film 108, the photo resist film 110 is processed so as to have a pattern, of the buried conductive layer, having a slit 110a on the gate electrode 105 by the photolithography method. Thereafter, the polycrystalline silicon film 108 is selectively etched away by the anisotropic dray etching with the photo resist film 110 as an etching mask, thereby processing the polycrystalline silicon film 108 so as to have a pattern which is separated into portions, located on the both sides of the gate electrode 105, with a width of the slit 110a. 
Next, as shown in FIG. 1E, the photo resist film 110 is removed. By carrying out the above-mentioned process, it is possible to form buried conductive layers 111, formed of the polycrystalline silicon film 108, which are respectively self-aligned with the pair of impurity diffusion layers 109 of the MOS transistor and each of which extends up to a upper portion of the gate electrode 105.
The buried conductive layers 111 are formed in such a way, whereby the alignment margin of the contact hole for the wiring connection which is formed through the insulating film on the associated buried conductive layer 111 can be increased and also the substantial aspect ratio of that contact hole can be decreased by a thickness of the associated buried conductive layer 111. As a result, it is possible to improve the reliability of the wiring connection in the contact hole portion. In addition, since the impurity diffusion layers 109 each having a shallower junction can also be formed, while suppressing occurrence of any crystal defect in the silicon substrate 101, by the thermal diffusion from the buried conductive layers 111, formation of the buried conductive layer 111 is also suitable for scale down of the semiconductor device.
Now, when forming the above-mentioned buried conductive layer 111, in the process shown in FIG. 1D, the slit 110a of the photo resist film 110 needs to be formed so as to reach the portion above the upper side of the gate electrode 105, and also a width thereof needs to be made much smaller than a width of the gate electrode 105 (a gate length).
This reason is that if due to the mismatch of alignment in the photolithography process, the central position of the slit of the photo resist film 110 is shifted in the direction of a width of the gate electrode by a distance X as shown in FIG. 2 for example so that the edge of the hole of the photo resist film 110 is located on the associated side wall oxide film 107, and under this condition, the polycrystalline silicon film 108 is subjected to the anisotropic etching, then not only the buried conductive layer 111 in the boundary portion between the buried conductive layer 111 of interest and the associated side wall oxide film 107 will be selectively etched away during the over-etching, but also the thin portion of the side wall oxide film 107 as well as the gate oxide film 103 will be etched away, and finally the surface of the silicon substrate 101 will be exposed.
Then, if the surface of the silicon substrate 101 is exposed, since the etch selectivity of the silicon substrate 101 to the buried conductive layer 111 formed of a polycrystalline silicon film is remarkably small, even the surface of the silicon substrate 101 will be partially etched away, and as a result, a trench 120 will be formed in the silicon substrate 101 by the etching. In such a way, the silicon substrate 101 will be damaged. Such damage of the silicon substrate 101 results in the performance of the MOS transistor being remarkably degraded.
In order to avoid that situation, the width of the slit 110a of the photo resist film 110 needs to be made much smaller than the gate length of the gate electrode 105 so as for the hole edge of the photo resist film 110 not be located on the associated side wall oxide film 107 even if the slight mismatch of alignment occurs. In other words, this means that the gate length of the gate electrode 105 needs to be made much larger than the width of the slit 110a of the photo resist film 110. Thus, even if the width of the slit 110a of the photo resist film 110 should be made a minimum processing size provided by the photolithography technology, the gate length of the gate electrode 105 needs to be made much larger than the minimum processing size. As a result, in the above-mentioned method of forming the buried conductive layer 111, there is a limit in scale down (shrink) of the transistor.
Now, in order to prevent the damage of the silicon substrate 101 due to the exposure of the surface of the silicon substrate 101, there is considered a method including the step of forming a polycrystalline silicon film, which will form a buried conductive layer later, after further forming an insulating film on the side wall oxide films, or a method including the step of forming a thicker side wall oxide film 107. However, in the former method, by the fine pattern technology, a hole needs to be formed through the insulating film formed on the associated side wall oxide film 107 so that contact is made between the buried conductive layer and the source/drain, and hence the advantage, resulting from the buried conductive layer, of being able to form the buried conductive layer so as to be self-aligned with the source/drain is lost. In addition, in the latter method, the width of each side wall oxide film 107 becomes necessarily large, and hence this results in the fine transistor not being able to be formed. Therefore, the above-mentioned two methods for preventing the damage of the silicon substrate 101 are not suitable for the practical use.
In addition, in JP-A-62-86715, there is described a method for manufacturing a semiconductor device wherein a contact hole is formed so as to be tapered in order to reduce the possibility of disconnection of the wiring layer.
Now, the manufacturing method described in JP-A-62-86715 will hereinbelow be described simply.
After a contact region having a predetermined pattern has been formed on a semiconductor substrate, an insulating layer is formed so as to cover the contact region. Next, a first photo resist mask is formed which is used to form a first contact hole, and then the insulating layer is etched to the depth of about one half of the thickness of the insulating layer by the anisotropic etching, thereby forming the first contact hole. Thereafter, the first photo resist mask is removed, and then a polycrystalline silicon layer is formed on the whole surface of the semiconductor substrate. Next, the whole surface of the polycrystalline silicon layer is selectively etched away by gas plasma so as to leave a part of the polycrystalline silicon layer on both an edge portion of the first contact hole and a stepped portion of the insulating film. Subsequently, a second photo resist mask is formed which is used to form a second contact hole, and then a second contact hole is formed through the insulating film remaining in the first contact hole by the etching.
While the above-mentioned manufacturing method is suitable for the scale down of the semi-conductor device, the etching by which the first contact hole is perforated needs to be stopped at the time when a thickness of the insulating layer has been halved, and hence the control of the etching amount is difficult to be carried out.
In view of the foregoing problems associated with the prior art, an object of the present invention is, in a semiconductor device having a baried conductive layer which is connected to a source/drain of a MOS transistor and which extends over a gate electrode of the MOS transistor, to enable a finer transistor as compared with the prior art transistor to be manufactured while preventing a semiconductor substrate from being damaged without complicating the manufacturing process excessively.
In order to attain the above-mentioned object, according to the present invention, there is provided a method for manufacturing a semiconductor device including the steps of: forming a first insulating film on a semiconductor substrate; forming a first conductive film as a gate electrode and a second insulating film on the first insulating film; forming a third insulating film on the whole surface of the semi-conductor substrate having the first insulating film, the first conductive film and the second insulating film formed thereon; selectively etching away the third insulating film so as to form a side wall insulating film including the third insulating film on each of both side faces of the first conductive film and the second insulating film and also to expose the semi-conductor substrate in portions which are not covered with both the side wall insulating film and the first conductive film; diffusing impurities into the exposed portions of the semiconductor substrate so as to form a source and a drain in the semiconductor substrate; forming a second conductive film to be a part of a buried conductive layer on the whole surface of the semiconductor substrate having the first insulating film, the first conductive film, the second insulating film and the side wall insulating film formed thereon; forming a first mask layer on the second conductive film; processing the first layer so as for the first mask layer to have a pattern which is separated into both side portions with the first conductive film; forming a second mask layer on the whole surface of the semiconductor substrate having the first insulating film, the first conductive film, the second insulating film, the side wall insulating film, the second conductive film and the first mask layer formed thereon; selectively etching away the second mask layer so as to leave a pattern of the second mask layer on each of both side faces of the pattern of the first mask layer; and selectively etching away the second conductive film with the patterns of the first and second mask layers as a mask so as to process the second conductive film into a pattern in which the second conductive film is separated on the second insulating film.
In addition, according to the present invention, there is provided a semiconductor device including: a semiconductor substrate having a source and a drain of a MOS transistor formed therein; a first insulating film formed on a predetermined region of the semiconductor substrate; a first conductive film as a gate electrode and a second insulating film formed on a predetermined region of the first insulating film; a third insulating film, as a side wall insulating film, formed on each of both side faces of the first conductive film and the second insulating film; a second conductive film connected to one of the source and the drain of the MOS transistor and extending up to a upper portion of the gate electrode of the MOS transistor, the second conductive film having a pattern in which the second conductive film is separated into both side portions with the second insulating film; a first mask layer formed on a first region of the second conductive film; and a second mask layer formed on a second region of the second conductive film along each of side faces of the first mask layer.
Now, after the second conductive film has been selectively etched away so as to be processed into a predetermined pattern, the first mask layer may be removed so that the resultant second conductive film is used as a lower electrode of a capacitor.
According to the present invention, since the first mask layer is formed on a region of a part of the second conductive film, and the second conductive film is selectively etched away with both the pattern of the first mask layer and the pattern of the second mask layer formed on each of the both side faces thereof as an etching mask, the interval of the patterns of the second conductive films which are adjacent to each other on the second insulating film can be made smaller than that of the patterns of the first mask layers by a width of the pattern of the second mask layer as compared with the interval. As a result, even if the position of the edge portion of the pattern of the first mask layer is slightly shifted, it is possible to reduce the probability that the edge portion of the pattern of the second conductive film is located on the associated side wall insulating film and hence it is possible to promote scale down (shrink) of the semiconductor device.
In addition, when the interval of the patterns of the first mask layers is made a minimum processing size in the photolithography technology, the interval of the patterns of the second mask layers can be made smaller than the minimum processing size. Therefore, the width of the first conductive film, i.e., the gate electrode can be made smaller than that of the prior art, e.g., it can be reduced down to the minimum processing size.
Incidentally, in the present invention, each of the first and second mask layers may be formed of either a conductive film or an insulating film. In the case where one or both of the first and second mask layer is formed of the conductive film, the mask layer of interest forms, together with the second conductive film, the buried conductive layer.